A Predistortion-less Digital MIMO Transmitter with DTC-Based Quadrature Imbalance Compensation

A four-element multi-input multi-output (MIMO) switched capacitor power amplifier (SCPA) in 22-nm fully depleted silicon-on-insulator (FD-SOI) is presented as a software-defined radio. To omit the digital predistortion (DPD) and digital quadrature correction power consumption of this wide modulation bandwidth MIMO transmitter, constant-conductance SCPA drivers and a wideband low-impedance power supply are used for linearization. dtc-based clock calibration is used for quadrature imbalance correction, improving image rejection to > 53 dB. This allows for up to 80-MHz DPD-less single carrier 1024-quadrature amplitude modulation (QAM) transmission, with an error vector magnitude (EVM) < − 39.4 dB. RF bandwidths up to 160 MHz are demonstrated for multicarrier 1024 QAM signals, supporting data rates up to 1.18 GBps. A second-order Chebyshev bandpass filter using bondwires as inductors is used as a matching network, supporting carrier frequencies from 1.64 to 3.28 GHz, while omitting the required chip area for integrated inductors. mimo experiments demonstrate the beamforming capabilities for single and multibeam communication

Power efficiency model for MIMO transmitters including memory polynomial digital predistortion

Multiple-input multiple-output (MIMO) beamforming array gain can make multi-antenna transmitters (TXs) more power efficient. However, these MIMO TXs require more complex digital predistortion (DPD). In this work, analytical expressions are derived for the power consumption of both MIMO power amplifier (PA) arrays and their respective DPD, taking into account the effects of precoding on PA output power and peak-toaverage power ratio (PAPR). It is shown that for complex DPD algorithms such as cross-over DPD (CO-DPD) in combination with wide bandwidths, the overall DPD power consumption can exceed the overall PA power consumption already for TXs for scenarios with more than two antennas

Analysis of Switched Capacitor Losses in Polar and Quadrature Switched Capacitor PAs

This paper derives the efficiency limitations of scpa due to sc losses during charging and discharging of their capacitor arrays. Polar modulation is covered, as well as quadrature modulation both with clock duty cycles of 50% ( q50q50) and 25% ( q25q25). Closed form expressions are derived for both the maximum output power and sc power loss for signals with arbitrary phase and amplitude. These expressions are verified by simulations using ideal switches and capacitors, and 22 nm CMOS transistor models. These results are used to analyze the scpa efficiency for 64QAM signals using a statistical model. It is shown that for a given array capacitance and supply voltage, the polar architecture is the most power efficient. Compared to polar modulation, the sc loss for 64QAM is fundamentally 18% higher for q50 and 46% higher for q25 scpa, whereas the generated output powers are fundamentally 6 and 3dB lower, respectively